We can use Cadence to automatically layout our standard cells. Starting from our our schematic window Tools >> Design Syn >> Layout Syn. LAS option will appear at the top schematic window. The following are all the changes that we have made when creating the standard cells. There many options avaiable, so you might want different settings.
2. Select LAS >> Generate
4. From this window we can select all the properties we want the layout of the standard cells to have.
Suggested Settings
Mode : Min. Area
Routing Style: V1H2
5. More Options
Height: 30
Width: -1 (-1 signifies that is not set and the cell can be arbitrarily wide)
These are the values used for the standard cells that are downloadable from this web page. If you want to have different sized standard cells, your number would be different of course
6. Pin
Check: Top and Bottom
Layer: M1
after the first Pin, hit "replace" and then "next" until all the pins are been changed.
This forces the pin to Metal 1, as done with the standard cells downloadable from this page. If you leave these fields blank, Cadence will try to optimize them.
7. Placement
Method: Optimized
Rows: 1
Transistor Width: See the picture below, this sets the maximum width of the FET before it is fingered. Value are in micro meters.
8. Routing
Over the Transistor Routing: None
This helps prevent DRC problems in the layout, also note you can change the N to P gate routing using either metal or poly
9. Power/Gnd
Merged Bus: check
Pwr/Gnd Seperation 28.8 um
Merged Width, see picture.
10. Process: No change
11. Now hit OK for Cadence to generate the layout.
12. Now the layout has been generated, however Cadence often makes some errors, thus we must fix the layout and run a DRC (design rule check) to make sure that the layout is correct. But first we must remove the outer yellow box. Seen selected below.
13. Now we will need to delete the them metal1 around the gnd wire.
14. Now we will run a DRC to see if there are any errors. The errors will be blinking on the layout. Often in my experience, some of the p-select or n-select is not 2 -lambda from active layer. Thus select the p-select from the materials column and then using the drawing tools, add p-select to the areas that are blinking.
14. Once the DRC has been performed and there are no errors, the layout is finished. One should look for this message in the Log.
15.One final thing needs to be done, Gnd, Vdd need to be streched untill the touch the outside of the metal, going to Edit >> stretch , or just hitting "s"
To:
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